| Rule Violations |
Count |
| Silk To Solder Mask (Clearance=0.254mm) (IsPad),(All) |
25 |
| Clearance Constraint (Gap=0.152mm) (IsVia),(IsSMTPin) |
0 |
| Clearance Constraint (Gap=0.152mm) (IsVia),(IsVia) |
0 |
| Parallel Segment Constraint (Gap=5.08mm ) (Limit=25.4mm) (All),(All) |
0 |
| Length Constraint (Min=0mm) (Max=1270mm) (All) |
2 |
| Parallel Segment Constraint (Gap=5.08mm ) (Limit=25.4mm) (All),(All) |
0 |
| Hole To Hole Clearance (Gap=0.152mm) (All),(All) |
32 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.381mm) (Air Gap=0.254mm) (Entries=0) (All) |
0 |
| Clearance Constraint (Gap=0.152mm) (All),(All) |
0 |
| SMD To Corner (Distance=0.152mm) (All) |
0 |
| Width Constraint (Min=0.152mm) (Max=0.508mm) (Preferred=0.35mm) (All) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
1 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
3 |
| Silk to Silk (Clearance=0.254mm) (All),(All) |
68 |
| Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.254mm) (All),(All) |
8 |
| Total |
139 |
